1. Field of the Invention
The present invention relates to a multiplier circuit for signal processing, such as an analog multiplier circuit and an analog divider circuit.
2. Description of the Related Art
As shown in FIG. 6, in a conventional analog multiplier circuit, a power-supply line 8 is connected to the collectors and bases of transistors Q.sub.A and Q.sub.B via a resistor R.sub.B. The power-supply line 8 is also connected to the collectors of transistors Q.sub.1 and Q.sub.2 via respective resistors R.sub.L. The emitters of transistors Q.sub.A and Q.sub.B are connected to the collectors of transistors Q.sub.3 and Q.sub.4, respectively, and are also connected to the bases of transistors Q.sub.1 and Q.sub.2, respectively. The emitters of transistors Q.sub.1 and Q.sub.2 are connected to the collector of transistor Q.sub.5. The emitters of transistors Q.sub.3 and Q.sub.4 are connected to the collectors of transistors Q.sub.6 and Q.sub.7, respectively. Between the collectors of transistors Q.sub.6 and Q.sub.7, a resistor r is connected. The base of transistor Q.sub.5 is connected to the base and collector of transistor Q.sub.8 and to an input terminal 1. The bases of transistors Q.sub. 6 and Q.sub.7 are connected to the base and collector of transistor Q.sub.9 and to an input terminal 2. The emitters of transistors Q.sub.6, Q.sub.7, and Q.sub.9 are connected to a ground line 3 via respective resistors R. The emitters of transistors Q.sub.5 and Q.sub.8 are connected to ground line 3 via respective resistors Re. Input terminals 4 and 5, across which an input voltage V.sub.in is applied, are connected to the bases of transistors Q.sub.3 and Q.sub.4, respectively. The collectors of transistors Q.sub.1 and Q.sub.2 are connected to output terminals 6 and 7, respectively.
FIG. 7 shows a logarithm compression/decompression circuit which is a component of the analog multiplier circuit shown in FIG. 6. In FIG. 7, transistors Q.sub.A, Q.sub.B, Q.sub.1, and Q.sub.2 are transistors which are all matched with each other so as to have the same characteristics. As to the transistors Q.sub.A, Q.sub.B, Q.sub.1, and Q.sub.2, respective collector currents (emitter currents) are represented by I.sub.A, I.sub.B, I.sub.1, and I.sub.2, and respective base-emitter voltages are represented by V.sub.BEA, V.sub.BEB, V.sub.BE1, and V.sub.BE2 (not shown).
The potential difference between base-emitter voltages V.sub.BEB and V.sub.BEA is obtained as follows: ##EQU1## where q denotes an electric charge of an electron, k denotes Boltzmann's constant, T is the absolute temperature, and I.sub.S denotes a reverse saturated current in the transistor Q.sub.A, Q.sub.B, Q.sub.1, and Q.sub.2. Also, the potential difference between base-emitter voltages V.sub.BE1 -V.sub.BE2 is represented as follows: EQU .DELTA.V.sub.BE(12) =V.sub.BE1 -V.sub.BE2 =(kT/q).multidot.ln (I.sub.1 /I.sub.2) (2)
Since the transistors Q.sub.A, Q.sub.B, Q.sub.1, and Q.sub.2 have identical characteristics, the values of .DELTA.V.sub.BE(AB) and .DELTA.V.sub.VBE(12) are equal to each other, so that the following is obtained from Equations (1) and (2): EQU I.sub.B /I.sub.A =I.sub.1 /I.sub.2 ( 3)
If Equation (3) is applied to the circuit of FIG. 6, the following equation is obtained: EQU (Ic-.DELTA.i)/(Ic+.DELTA.i)=(Ie-.DELTA.I)/(Ie+.DELTA.I) EQU .DELTA.I=(Ie/Ic).multidot..DELTA.i
Herein, since .DELTA.i=V.sub.in /r, and V.sub.out =2.multidot.R.sub.L .multidot..DELTA.I, the following is obtained: EQU V.sub.out =2.multidot.(R.sub.L /r).multidot.(Ie/Ic).multidot.V.sub.in
Accordingly, the output voltage V.sub.out is a differential output in proportion to the product of the differential input voltage V.sub.in and Ie/Ic.
However, in such a conventional circuit in which the emitter resistors R or Re are provided between the respective transistors Q.sub.5, Q.sub.6, Q.sub.7, Q.sub.8, and Q.sub.9 and ground, a supply voltage of 4.multidot.V.sub.BE or more is required in order to apply 1.multidot.V.sub.BE across the base and emitter of respective transistors Q.sub.5, Q.sub.6, Q.sub.7, Q.sub.8, and Q.sub.9, because the circuit in FIG. 6 includes transistors of 3 stages in cascade in series with the emitter resistors R or Re. In the case of a silicon transistor, V.sub.BE is about 0.7 V, voltage between the emitter resistor R or Re is about 0.7 V so that a supply voltage of 2.8 V (4.multidot.V.sub.BE) or more is required. In order to operate at a voltage lower than 2.8 V, the dynamic range of the circuit would be significantly reduced. Also, if the supply voltage is as low as 3.multidot.V.sub.BE, the dynamic range is virtually lost, and the signals may disadvantageously be distorted.